From Contamination to Defects, Faults and Yield Loss: Simulation and Applications

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Contents

  1. Simulation and Applications
  2. IN ADDITION TO READING ONLINE, THIS TITLE IS AVAILABLE IN THESE FORMATS:
  3. Figure 9 from Simulation of yield/cost learning curves with Y4 - Semantic Scholar
  4. From Contamination to Defects, Faults and Yield Loss

The measured signatures distribution can be inverted with help of the knowledge base matrix to yield the relative contribution of each process layer to the failures observed. Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons having the benefit of this disclosure.

A method for determining the integrated circuit manufacturing operations that are the principle contributors to defect limited test yield loss comprises extracting the electrical faults for the important range of defect sizes from the layout data base; determining the signatures of the electrical response of faulted circuits to the input test stimuli; determining the statistical frequency distribution of the signatures for a fixed ratio of defect densities on the several process layers; determining the frequency distribution of the signatures observed in testing a wafer or group of wafers; and adjusting the defect densities amongst the process layers to minimize the difference between the predicted and observed frequency distributions such that the adjusted defect distribution provides a measure of the relative contribution of the process layers to yield loss.

The actions depicted in the blocks 10 , 12 , 14 , 16 , 18 , and 22 in FIG. The actions in the blocks 24 and 26 in FIG. The first thing that must be done is to determine where and with what probability defects of differing sizes can cause faults to occur on or between process layers. This is accomplished at block 10 of FIG. Clearly not all defects can cause defects at all locations. It should be clear that defects smaller than the minimum feature size cannot lead to bridging faults because they are too small to bridge adjacent lines that have even the minimum spacing.

Simulation and Applications

Such defects are also too small to cause breaks in a line because the cross section of the smallest line exceeds the defect size. It is also well known that the probability of defects occurring is proportional to 1-a where 1 is the defect size and a is a positive parameter that is found empirically to be about 3. The range of defects size between the minimum feature size and about 4 times the minimum feature size is referred to as the fault-causing range of defects because most faults are caused by defects in this size range.

For example, a bridging defect that is smaller than the minimum spacing between two traces on a layer can not bridge the two traces. If the bridging defect is larger than the minimum spacing between the two traces, it may cause a fault, depending on where the defect is located. As is illustrated in FIG. This locus of points 30 is called the critical area. Although illustrated here for an idealized circular defect, persons of ordinary skill in the art this concept can be generalized. The probability that a defect will cause a fault is proportional to the critical area of the defect for that fault.

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Thus, calculation of the critical areas for the various possible faults provides a relative measure of the fault probabilities. Those of ordinary skill in the art are well aware of several methods of computing the critical areas of a given layout for defects of a selected size. Once the critical areas are determined for each layer as a function of defect size, these results are stored at block Next, at block 14 , the electrical test stimuli to be used are applied to the IC under test.


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The signatures depend on the electrical tests that are employed which are, in turn, dependent upon the type of IC being tested. If the IC were a logic part, the test would consist of a series of test vectors i. In the case that the IC is a memory, the test usually consists of writing and reading a number of data patterns to and from the IC under test. This is often done at several different supply voltages and possibly at more than one temperature. While the test methodology varies with the device to be tested, this is a subject that has been studied extensively for all commercially imported circuit types and is very well known to persons of ordinary skill in the art.

In the case where the IC is a memory, the test usually consists of writing and reading a number of data patterns to and from the IC under test. For logic testing, the number of input and output vectors are generally the same, but the size of the vectors i. For this case the signatures might be as detailed as all of the output levels for all of the vectors, but more likely would be a compression of this information.

The compressed. The compression algorithm could also take a large number of other forms that would offer either more compression, more detail or both as will be apparent to one of ordinary skill in the art. It is likely that the patterns would be compressed for the memory case also. For the example in this disclosure, it will be assumed that the signatures take the form of a geometrical description of the pattern of the failing bits summed over all of the tests, e.

At block 16 , the responses to the electrical test stimuli are collected. Knowing the possible faults in the IC or section of the IC under test, and the electrical stimuli to be used in the test, the responses of the faulted ICs to the test vectors can be determined by one of several ways well known in the art. For example, the responses could be determined with a analog circuit simulator, such as the well-known SPICE simulator, or with a logic simulator, e.

This is discussed, for example, in D. They can also be determined with a heuristic algorithm as will be described later. The signatures are found for the faults on each layer or set of layers individually for a range of defect sizes. A range of defect sizes is a fixed ratio of defect densities on each process layer. The defect density being the amount of defects in a layer. The defect sizes are chosen to match those expected to be important for the process technology used for the IC to be tested.

For example, bridging defects less than the minimum feature spacing can be ignored, and it is known that the probability of a defect decreases rapidly with defect size.

For defect size distributions like this, defect sizes ranging from about the minimum feature size to about four times the minimum feature size capture most of the important features. Once the critical area associated with each fault has been found, and the signatures from the faults found, the statistical frequency distribution of the signatures can be found for each layer. These responses are sorted so that the critical areas of all faults on a given process layer with the same signature are combined and stored as those of a common failure signature.

This is illustrated at block See, for example, Charles H. The critical areas for the different defect sizes are multiplied by a factor proportional to the probability of defects of that size occurring and then the signatures are summed over defect sizes for each process layer or set of process layers to yield the signature distribution for each layer. Mathematically speaking, there are m signatures into which the failing devices are classified. Examples of signatures for a memory are single bits, paired bits, rows, columns, etc.

Lecture 56: Fault Modeling

There are n layers, or layer combinations, that can cause a fault. Examples of single-layer faults are metal- 1 breaks or poly bridges. Examples of two-layer faults are metal- 1 -to-poly shorts or poly-to-active shorts through the gate oxide.

Figure 9 from Simulation of yield/cost learning curves with Y4 - Semantic Scholar

All faults on a given layer fall into one of the signatures. The actual number of faults that occur depends on the absolute defect density, but the relative number of faults on each layer, defined by. This information is stored at block 22 for application to the test results. After the test stimuli are applied to a wafer or set of wafers, the failing ICs are classified as to their failure signatures by measuring the signature distribution on the wafer or set of wafers at block The number of wafers in the test lot should be large enough that the number of signatures classified is large enough to be statistically significant.

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From Contamination to Defects, Faults and Yield Loss

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However, for aseptic filling conducted in an isolator over two shifts, it may be justified to perform fewer than four media fill runs per year, while still evaluating the line semiannually to ensure a continued state of aseptic process control. This lower total number of media fill runs would be based on sound risk rationale and would be subject to reevaluation if contamination issues e. Why is FDA concerned about human topical antiseptic drug products?

FDA has identified several incidents of objectionable microbial contamination of topical antiseptic drug products e. Microbial contamination may be caused by substandard manufacturing practices, and the Agency is concerned about safety risks, such as from infection, associated with this contamination. What specific CGMP regulations might be useful to manufacturers of topical antiseptic drug products? Some relevant CGMP regulations, with a brief description, are given below:. How can manufacturers assess and address the risk of microbiological contamination of topical antiseptics?

Because there are potentially many different root causes of product contamination by microorganisms, it is imperative that manufacturers perform a manufacturing risk assessment to understand manufacturing failure modes and implement prevention measures. In addition, any risk assessment approach should be informed by an understanding of the microbial contamination vulnerabilities of the concerned product.

For example, some product considerations for manufacturers include, but are not limited to:.


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Can Leptospira species penetrate sterilizing-grade filters? If so, what should manufacturers keep in mind in their ongoing lifecycle risk management efforts to ensure microbial control? There is no indication that this bacterium ultimately contaminated either the finished drug substance or drug product. This bacterium has been found to pass through 0. While this specific species was the identified contaminant in this case, other Leptospira species also are capable of passing through 0. Compendial microbiological test methods typically used in association with upstream biotechnology and pharmaceutical production are not capable of detecting this type of bacteria.

Whether this apparently rare contamination risk may be more widespread is unknown, and we are sharing this information so that manufacturers can consider whether this hazard may be relevant to their operations. Leptospira are Gram-negative aerobic spirochetes that are flexible, highly motile, and spiral-shaped with internal flagella.